1. Field of the Invention
The invention relates to the field of semiconductor dynamic memories.
2. Prior Art
Metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) dynamic random-access memories (DRAMs) continue to increase in density from, for example, the 1K memories of the late 1960's to the currently used 64K memories of today. The described invention is realized in a 256K CMOS memory, although the inventive concepts described may be utilized in other size memories.
In DRAMS, typically memory cells each of which include a single transistor and capacitor, are coupled to bit lines. Pairs of bit lines extend from a latch-like sense amplifier. Dummy cells, restore circuits, and architecture employing folded bit lines are commonly used in current DRAMs.
The capacity of an MOS DRAM can, of course, be increased by employing more memory cells. But unless higher density fabrication is used, that is, smaller cells, etc., the higher capacity memories are not suited for high volume production because the increased substrate area decreases yields. There is, thus, always the continuing goal to shrink the size of the memory cells. However, as the cells are made smaller, they store less charge and it becomes increasingly difficult to sense the binary state stored in the cells. It is easier to sense a smaller cell if the bit line capacitance is reduced and this can be achieved with fewer cells on the bit lines allowing them to be shortened. On the other hand, where greater array effeciency is sought, it is helpful if more cells are placed along each of the bit lines. Using shorter bit lines require more sense amplifiers, consequently, some of the increased density gained by using smaller cells with shorter bit lines can be lost because of the additional sense amplifiers and related peripheral circuit (e.g., decoders).
One prior art suggestion, although not commercialized, is to multiplex pairs of bit lines to a single sense amplifier. This technique, in theory, permits use of the shortened bit lines without requiring additional sense amplifiers. The present invention employs this technique, but not in the manner used in the prior art. For instance, with the present invention, as will be seen, there is a decoupling of the bit lines from the sense amplifier when sensing occurs.
In some prior art DRAMs, bit lines are precharged to the full power supply potential, for example, five volts. In others, the bit lines are charged to a reference potential such as half the power supply potential. These precharging techniques are used both with and without dummy cells. An obvious advantage to charging to one-half the power supply potential is that the memory consumes less power. However, there are a number of problems with this system. In one case, the bit lines are precharged during an inactive cycle. The power supply potential can vary between the time of the precharging and the actual sensing and this variation causes difficulty in sensing. Another problem with precharging the bit lines to half the power supply potential is that poor performance results when the power supply potential is low. With the described invention, the bit lines are charged to half the power supply potential in a unique way and in combination with the multiplexing mentioned above. Not only is less power consumed, but also the peak currents are reduced with the present invention.
For recent discussions of DRAM technology, see (1) "A 90NS 256K.times.1B DRAM With Double Level AL Technology", ISSCC Digest of Technical Papers pages 226-227, Feb. 1983, by Fujii, T. et al; (2) "A 64 Kb CMOS RAM", ISSCC Digest of Technical Papers pages 258,259, Feb. 1982, by Konishi, S. et al, (3) "A 70NS High Density CMOS DRAM", ISSCC Digest of Technical Papers pages 56-57, Feb. 1983, by Chwang, R. et al; (4) "A 100 ns 5 V Only 64K.times.1 MOS Dynamic RAM", IEEE Journal of Solid-State Circuits pp. 839-845, Vol. SC-15, No. 5. Oct. 1980 by Chan, J. et al; and (5) "A 5V-Only 64K Dynamic RAM Based on High S/N Design", IEEE Journal of Solid-State Circuits p. 846, Vol. SC-15, No. 5, Oct. 1980 by Masuda, H. et al.